1. Field of the Invention
The present invention relates to the field of semiconductor devices. More particularly, the present invention provides an improved method and apparatus for reducing impedance in a semiconductor package.
2. In the field of semiconductor device manufacture, it is necessary to provide a connection from an integrated circuit to the "outside world." This function is typically performed by a semiconductor package which may be, for example, a DIP or PLCC which includes 40 or more leads used for signal transmission and power transmission. In addition to transferring signals, power, and the like to the outside world, the package also serves to protect the integrated circuit from environmental effects and provide heat dissipation.
As integrated circuit speeds and packing densities increase, the importance of the packaging technology becomes increasingly significant. For example, as devices approach gigahertz speed, inductance effects and the like in the packaging become significant. Such inductance effects may arise from, for example, switching and the like, and are particularly problematic in power and ground leads. Inductance effects in the package can cause ground bounce, signal cross-talk, and the like. Increasing circuit size and speed also impact the heat dissipation ability of the packaging.
A variety of solutions to inductance problems in integrated circuit packaging have been proposed. For example, Daniels et al., U.S. Pat. No. 4,680,613, disclose a low impedance dual in-line package in which a dielectric layer is provided adjacent a lead frame and a ground plate is provided adjacent the dielectric layer. A ground lead finger is electrically connected in parallel to the ground plate and a decoupling capacitor is provided between the ground plate and a downset tab on the power lead. The integrated circuit rests upon the ground plate and is attached thereto via a die pad of the chip.
The packaging method and apparatus disclosed in Daniels et al. have a number of disadvantages. For example, it becomes necessary to re-tool existing packaging fabrication facilities to manufacture packaging in accord with the devices disclosed in Daniels et al. since the lead frame and the like are non-standard. Further, the decoupling capacitor is placed between the lead frame and the ground plane. Consequently, placement of the decoupling capacitors in the package becomes difficult. Further, there is only one low impedance path in the package disclosed by Daniels et al., whereas at least two low inductance paths are needed for ground and power supply interconnects in integrated circuits.
Other packaging techniques are described in, for example, Hyslop et al., "High Performance Decoupling Capacitor for Installation Under the Dual-In-Line IC Package," Proceedings of the 37th Electronic Components Conference (1987), and Biswas, "A New Concept in Decoupling I.C. Devices," Sixteenth Annual Connectors and Interconnection Technology Symposium Proceedings (1983).
From the above it is seen that an improved packaging apparatus and method of fabrication thereof is desired.